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PCA9620
Universal LCD driver for low multiplex rates
Rev. 1 -- 9 December 2010 Product data sheet
1. General description
The PCA9620 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD)1 with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to eight backplanes, 60 segments, and up to 480 elements. The PCA9620 is compatible with most microprocessors or microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized using a display RAM with auto-incremented addressing and display memory switching. The PCA9620 features an internal charge pump with internal capacitors for on-chip generation of the LCD driving voltages. AEC Q100 grade 2 compliant for automotive applications.
2. Features and benefits
Low power consumption Extended operating temperature range from -40 C to +105 C 60 segments and 8 backplanes allowing to drive: up to 60 7-segment alphanumeric characters up to 30 14-segment alphanumeric characters any graphics of up to 480 elements 480 bit RAM for display data storage Selectable backplane drive configuration: static, 2, 4, 6, or 8 backplane multiplexing Programmable internal charge pump for on-chip LCD voltage generation up to 3 x VDD2 400 kHz I2C-bus interface Selectable linear temperature compensation of VLCD Selectable display bias configuration Wide range for digital and analog power supply: from 2.5 V to 5.5 V Wide LCD supply range: from 2.5 V for low threshold LCDs and up to 9.0 V for high threshold (automobile) twisted nematic LCDs Display memory bank switching in static, duplex, and quadruplex drive modes Programmable frame frequency in steps of 10 Hz in the range of 60 Hz to 300 Hz; factory calibrated with a tolerance of 15 % covering the whole temperature and voltage range Selectable inversion scheme for LCD driving waveforms: frame or line inversion Integrated temperature sensor with temperature readout On chip calibration of internal oscillator frequency and VLCD
1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 15 on page 65.
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PCA9620
Universal LCD driver for low multiplex rates
3. Ordering information
Table 1. Ordering information Package Name PCA9620H LQFP80 Description plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm Version SOT315-1 Type number
4. Marking
Table 2. PCA9620H Marking codes Marking code PCA9620H/Q900 Type number
5. Block diagram
VLCD BP0 to BP7 S0 to S59
60 VDD2 BACKPLANE OUTPUTS LCD VOLTAGE SELECTOR DISPLAY CONTROL LCD BIAS GENERATOR DISPLAY SEGMENT OUTPUTS
CHARGE PUMP(1) (VOLTAGE MULTIPLIER)
DISPLAY REGISTER
OUTPUT BANK SELECT
VSS
DISPLAY RAM TEMPERATURE SENSOR CLOCK SELECT AND TIMING
PCA9620
CLK
OSCILLATOR
POWER-ON RESET
COMMAND DECODER
WRITE DATA CONTROL
DATA POINTER, AUTO INCREMENT
SCL SDA
INPUT FILTERS
I2C-BUS CONTROLLER
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A0
A1
VDD1
T1 T2 T3
(1) The charge pump can generate a maximum output voltage of 3 x VDD2.
Fig 1.
Block diagram of PCA9620
PCA9620
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Universal LCD driver for low multiplex rates
6. Pinning information
6.1 Pinning
80 S19 79 S18 78 S17 77 S16 76 S15 75 S14 74 S13 73 S12 72 S11 71 S10 70 S9 69 S8 68 S7 67 S6 66 S5 65 S4 64 S3 63 S2 62 S1 61 S0
S20 S21 S22 S23 S24 S25 S26 S27 S28
1 2 3 4 5 6 7 8 9
60 SDA 59 SCL 58 A1 57 A0 56 CLK 55 T3 54 T2 53 T1 52 VSS 51 VDD1 50 VDD2 49 VLCD 48 BP7 47 BP6 46 BP5 45 BP4 44 BP3 43 BP2 42 BP1 41 BP0
S29 10 S30 11 S31 12 S32 13 S33 14 S34 15 S35 16 S36 17 S37 18 S38 19 S39 20
PCA9620
S40 21
S41 22
S42 23
S43 24
S44 25
S45 26
S46 27
S47 28
S48 29
S49 30
S50 31
S51 32
S52 33
S53 34
S54 35
S55 36
S56 37
S57 38
S58 39
S59 40
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Top view. For mechanical details, see Figure 57 on page 61.
Fig 2. Pin configuration for LQFP80 (PCA9620H)
PCA9620
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6.2 Pin description
Table 3. Symbol S0 to S59 BP0 to BP7 VLCD VDD2 VDD1 VSS T1 to T3 CLK A0, A1 SCL SDA
[1]
Pin description Pin 61 to 80 and 1 to 40 41 to 48 49 50 51 52 53 to 55 56 57, 58 59 60 Type output output supply supply supply input input/output input input input/output Description LCD segment LCD backplane supply voltage 2 (charge pump) supply voltage 1 (analog and digital) ground supply voltage test pins; must be tied to VSS in applications internal oscillator output, external oscillator input I2C-bus slave address selection bit I2C-bus serial clock I2C-bus serial data
supply/output[1] LCD supply voltage
When the internal VLCD generation is used, this pin drives the VLCD voltage. In this case pin VLCD is an output. When the external supply is requested then pin VLCD is an input and VLCD can be supplied to it. In this case the internal charge pump must be disabled (see Table 8 on page 7).
PCA9620
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PCA9620
Universal LCD driver for low multiplex rates
7. Functional description
The PCA9620 is a versatile peripheral device designed to interface any microprocessor or microcontroller to a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to 480 elements.
7.1 Commands of PCA9620
The PCA9620 is controlled by 22 commands, which are defined in Table 4. Any other combinations of operation code bits that are not mentioned in this document may lead to undesired operation modes of PCA9620.
Table 4. Commands of PCA9620 Bits 7 initialize OTP-refresh oscillator-ctrl charge-pump-ctrl temp-msr-ctrl temp-comp-SLA temp-comp-SLB temp-comp-SLC temp-comp-SLD set-VPR-MSB set-VPR-LSB display-enable set-MUX-mode set-bias-mode load-data-pointer frame-frequency input-bank-select output-bank-select write-RAM-data temp-read invmode_CPF_ctrl temp-filter 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 B[7:0] TD[7:0] 1 1 1 1 0 0 1 1 0 0 1 0 LF 1 CPF TFE 6 0 1 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 0 5 1 0 0 0 0 0 1 1 1 0 0 1 0 0 P[5:0] 1 0 0 F[4:0] 0 1 1 0 IB[2:0] OB[2:0] Section 7.1.13 Section 7.1.14, Section 7.4.7 Section 7.1.15 Section 7.1.16 4 1 1 0 0 0 1 0 0 1 0 1 1 0 0 3 1 0 1 0 1 1 0 1 0 2 0 0 1 0 0 1 1 0 COE CPE TCE 0 0 0 OSC CPC TME Section 7.1.1 Section 7.1.2 Section 7.1.3 Section 7.1.4 Section 7.1.5 Table 29 Reference
Command name
SLA[2:0] SLB[2:0] SLC[2:0] SLD[2:0]
VPR[7:4] VPR[3:0] 1 0 0 0 M[2:0] 1 B[1:0] 0 E
Section 7.1.6 Section 7.1.7 Section 7.1.8 Section 7.1.9 Section 7.1.10 Section 7.1.11 Section 7.1.12.1
7.1.1 Command: initialize
This command generates a chip wide reset which resets all command values to their default values (see Table 25 on page 15). It must be sent to the PCA9620 after power-on. After this command is sent, it is possible to send additional commands without the need to re-initialize the interface. Reset takes 100 ns to complete. For further information see Section 7.3 on page 14.
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Initialize - initialize command bit description Symbol Value 00111010 Description fixed value
Table 5. Bit 7 to 0
7.1.2 Command: OTP-refresh
During production and testing of the device, each IC is calibrated in order to achieve the specified accuracy of VLCD, the frame frequency, and the temperature measurement. This calibration is performed on EPROM cells called One Time Programmable (OTP) cells. These cells are being read by the device at power-on, after a reset, and every time when the initialize command or the OTP-refresh command is sent. This command will take approximately 10 ms to finish.
Table 6. Bit 7 to 0 OTP-refresh - OTP-refresh command bit description Symbol Value 11010000 Description fixed value
7.1.3 Command: oscillator-ctrl
The oscillator-ctrl command switches between internal and external oscillator and enables or disables pin CLK.
Table 7. Oscillator-ctrl - oscillator control command bit description For further information, see Section 7.5 on page 38. Bit 7 to 2 1 Symbol COE 0[1] 1 0 OSC 0[1] 1
[1] Default value.
Value 110011
Description fixed value control pin CLK clock signal not available on pin CLK; pin CLK is in 3-state and may be left floating clock signal available on pin CLK oscillator source internal oscillator running external oscillator used; pin CLK becomes an input
PCA9620
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7.1.4 Command: charge-pump-ctrl
The charge-pump-ctrl command enables or disables the internal VLCD generation and controls the charge pump voltage multiplier setting.
Table 8. Bit 7 to 2 1 CPE 0[1] Charge-pump-ctrl - charge pump control command bit description Symbol Value 110000 Description fixed value charge pump switch charge pump disabled; no internal VLCD generation; external supply of VLCD charge pump enabled charge pump voltage multiplier setting 0[1] 1
[1] Default value.
1 0 CPC
VLCD = 2 x VDD2 VLCD = 3 x VDD2
7.1.5 Command: temp-msr-ctrl
The temp-msr-ctrl command enables or disables the temperature measurement block and the temperature compensation of VLCD.
Table 9. Temp-msr-ctrl - temperature measurement control command bit description For further information, see Section 7.4.8 on page 36. Bit 7 to 2 1 Symbol TCE 0 1[1] 0 TME 0 1[1] Value 110010 Description fixed value temperature compensation switch no temperature compensation of VLCD possible temperature compensation of VLCD possible temperature measurement switch temperature measurement disabled; no temperature readout possible temperature measurement enabled; temperature readout possible
[1] Default value.
7.1.6 Command: set-VPR-MSB and set-VPR-LSB
With these two instructions it is possible to set the target VLCD voltage for the internal charge pump, see Section 7.4.3 on page 31.
Table 10. Bit 7 to 4 3 to 0
[1]
Set-VPR-MSB - set VPR MSB command bit description Symbol VPR[7:4] Value 0100 0000[1] Description fixed value to 1111 the four most significant bits of VPR[7:0]
Default value.
PCA9620
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Set-VPR-LSB - set VPR LSB command bit description Symbol VPR[3:0] Value 0101 0000[1] Description fixed value to 1111 the four least significant bits of VPR[7:0]
Table 11. Bit 7 to 4 3 to 0
[1]
Default value.
7.1.7 Command: display-enable
Table 12. Bit 7 to 1 0 E Display-enable - display enable command bit description Symbol Value 0011100 0[1] Description fixed value display disabled; backplane and segment outputs are internally connected to VSS display enabled
1
[1] Default value.
7.1.8 Command: set-MUX-mode
Table 13. Bit 7 to 3 2 to 0 M[2:0] Set-MUX-mode - set multiplex drive mode command bit description Symbol Value 00000 000[1], 011, 110, 111 001 010 100 101
[1] Default value.
Description fixed value 1:8 multiplex drive mode: 8 backplanes static drive mode: 1 backplane 1:2 multiplex drive mode: 2 backplanes 1:4 multiplex drive mode: 4 backplanes 1:6 multiplex drive mode: 6 backplanes
7.1.9 Command: set-bias-mode
Table 14. Bit 7 to 2 1 to 0 B[1:0] Set-bias-mode - set bias mode command bit description Symbol Value 110001 00[1], 11 10
[1] Default value.
Description fixed value
1 1 1 4 3 2
01
bias bias bias
7.1.10 Command: load-data-pointer
The load-data-pointer command defines one of the 60 display RAM addresses where the following display data will be sent to. For further information, see Section 7.9.1 on page 41.
PCA9620
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Universal LCD driver for low multiplex rates
Load-data-pointer - load data pointer command bit description Symbol P[5:0] Value 10 000000 to 111111 Description fixed value 6-bit binary value of 0 to 59
Table 15. Bit 7 to 6 5 to 0
7.1.11 Command: frame-frequency
With the frame-frequency command the frame frequency and the output clock frequency can be configured.
Table 16. Bit 7 to 5 4 to 0 Table 17. F[4:0] 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110[3] 01111 10000 10001 10010 10011 10100, 10101 10110, 10111 11000 to 11111
[1] [2] [3]
PCA9620
Frame frequency - frame frequency and output clock frequency command bit description Symbol F[4:0] Value 011 see Table 17 Description fixed value nominal frame frequency (Hz)
Frame frequency values Nominal frame frequency, ffr (Hz)[1] 60 70 80 91 100 109 120 129.7 141.2 150 160 171.4 177.8 192 200 208.7 218.2 228.6 240 252.6 266.7 282.4 300 Resultant oscillator frequency, fosc (Hz) 2880 3360 3840 4368 4800 5232 5760 6226 6778 7200 7680 8227 8534 9216 9600 10018 10474 10973 11520 12125 12802 13555 14400 Duty cycle (%)[2] 20 : 80 7 : 93 47 : 53 40 : 60 33 : 67 27 : 73 20 : 80 13 : 87 5 : 95 50 : 50 47 : 53 43 : 57 41 : 59 36 : 64 33 : 67 30 : 70 27 : 73 23 : 77 20 : 80 16 : 84 10 : 90 5 : 95 50 : 50
Nominal frame frequency calculated for the default clock frequency of 9600 Hz. Duty cycle definition: % HIGH-level time : % LOW-level time. Default value.
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7.1.12 Bank select commands
For multiplex drive modes 1:4, 1:2 and static drive mode, it is possible to write data to one area of the RAM whilst displaying from another. These areas are named as RAM banks. Input and output banks can be set independently from one another with the input-bank-select and the output-bank-select command. For further information see Section 7.9.2 on page 46. 7.1.12.1 Command: input-bank-select
Table 18. Bit 7 to 3 2 to 0 IB[2:0] 000[2] 001 010 011 100 101 110 111
[1] [2]
Input-bank-select - input bank select command bit description[1] Symbol Value 00001 Description fixed value selects RAM bank to write to static drive mode bank 0: RAM-row 0 bank 1: RAM-row 1 bank 2: RAM-row 2 bank 3: RAM-row 3 bank 4: RAM-row 4 bank 5: RAM-row 5 bank 6: RAM-row 6 bank 7: RAM-row 7 1:2 drive mode bank 0: RAM-rows 0 and 1 bank 2: RAM-rows 2 and 3 bank 4: RAM-rows 4 and 5 bank 6: RAM-rows 6 and 7 bank 4: RAM-rows 4, 5, 6, and 7 1:4 drive mode bank 0: RAM-rows 0, 1, 2, and 3
Not applicable for multiplex drive mode 1:6 and 1:8. Default value.
7.1.12.2
Command: output-bank-select
Table 19. Bit 7 to 3 2 to 0 OB[2:0] 000[2] 001 010 011 100 101 110 111
[1] [2]
Output-bank-select - output bank select command bit description[1] Symbol Value 00010 Description fixed value selects RAM bank to read from to the LCD static drive mode bank 0: RAM-row 0 bank 1: RAM-row 1 bank 2: RAM-row 2 bank 3: RAM-row 3 bank 4: RAM-row 4 bank 5: RAM-row 5 bank 6: RAM-row 6 bank 7: RAM-row 7 1:2 drive mode bank 0: RAM-rows 0 and 1 bank 2: RAM-rows 2 and 3 bank 4: RAM-rows 4 and 5 bank 6: RAM-rows 6 and 7 bank 4: RAM-rows 4, 5, 6, and 7 1:4 drive mode bank 0: RAM-rows 0, 1, 2, and 3
Not applicable for multiplex drive mode 1:6 and 1:8. Default value.
PCA9620
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7.1.13 Command: write-RAM-data
The write-RAM-data command writes data byte-wise to the RAM. After Power-On Reset (POR) the RAM content is random and should be brought to a defined status by clearing it (setting it logic 0).
Table 20. Bit 7 to 0
[1]
Write-RAM-data - write RAM data command bit description[1] Symbol B[7:0] Value 00000000 to 11111111 Description writing data byte-wise to RAM
For this command bit RS of the control byte has to be set logic 1 (see Table 33 on page 52).
More information about the display RAM can be found in Section 7.9 on page 40.
7.1.14 Command: temp-read
The temp-read command allows reading out the temperature values measured by the internal temperature sensor.
Table 21. Temp-read - temperature readout command bit description[1] For further information, see Table 9 on page 7 and Section 7.4.7 on page 35. Bit 7 to 0
[1]
Symbol TD[7:0]
Value 00000000 to 11111111
Description readout representing the digital temperature
For this command bit R/W of the I2C-bus slave address byte has to be set logic 1 (see Table 32 on page 51).
7.1.15 Command: invmode_CPF_ctrl
The invmode_CPF_ctrl command allows changing the drive scheme inversion mode and the charge pump frequency. The waveforms used to drive LCD displays inherently produce a DC voltage across the display cell. The PCA9620 will compensate for the DC voltage by inverting the waveforms on alternate frames or alternate lines. The choice of compensation method is determined with the LF bit.
Table 22. Bit 7 to 2 1 Invmode_CPF_ctrl - inversion mode and charge pump frequency prescaler command bit description Symbol LF 0[1] 1 0 CPF 0[1] 1
[1] Default value.
Value 110101
Description fixed value set inversion mode line inversion mode frame inversion mode set charge pump oscillator frequency fosc(cp) ~ 1 MHz fosc(cp) ~ 500 kHz
PCA9620
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In frame inversion mode the DC value is compensated across two frames and not within one frame. Changing the inversion mode to frame inversion reduces the power consumption, therefore it is useful when power consumption is a key point in the application. Frame inversion may not be suitable for all applications. The RMS voltage across a segment is better defined, however since the switching frequency is reduced there is possibility for flicker to occur. The waveforms of Figure 15 on page 23 to Figure 21 on page 29 are showing line inversion mode. Figure 22 on page 30 shows one example of frame inversion.
7.1.16 Command: temp-filter
Table 23. Bit 7 to 1 0 TFE 0[1] Temp-filter - digital temperature filter command bit description Symbol Value 1101001 Description fixed value digital temperature filter switch digital temperature filter disabled; the unfiltered digital value of TD[7:0] is immediately available for the readout and VLCD compensation, see Section 7.4.7 on page 35 digital temperature filter enabled
1
[1] Default value.
7.2 Possible display configurations
The PCA9620 is a versatile peripheral device designed to interface between any microprocessor or microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 3). It can directly drive any static or multiplexed LCD containing up to eight backplanes and up to 60 segments. The display configurations possible with the PCA9620 depend on the number of active backplane outputs required; a selection of possible display configurations is given in Table 24.
PCA9620
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dot matrix
7-segment with dot
14-segment with dot and accent
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Fig 3. Table 24.
Example of displays suitable for PCA9620 Selection of possible display configurations Icons 480 320 240 120 60 Digits/Characters 7-segment 14-segment 30 22 15 7 3 60 45 30 15 7 Dot matrix/ Elements 480 dots (8 x 60) 360 dots (6 x 60) 240 dots (4 x 60) 120 dots (2 x 60) 60 dots (1 x 60)
Number of Backplanes 8 6 4 2 1
All of the display configurations in Table 24 can be implemented in the typical systems shown in Figure 4 (internal VLCD) and in Figure 5 (external VLCD).
VDD1
VDD2
R
tr 2Cb VDD1 VDD2 VLCD
60 segment drives
HOST PROCESSOR/ MICROCONTROLLER
SDA SCL PCA9620
LCD PANEL (up to 480 elements)
8 backplanes
A0
A1
CLK n.c.
VSS
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VSS
VDD1 from 2.5 V to 5.5 V and VDD2 from 2.5 V to 5.5 V.
Fig 4.
Typical system configuration when using the internal VLCD generation
PCA9620
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Universal LCD driver for low multiplex rates
VDD1
VLCD
R
tr 2Cb VDD1 VDD2 VLCD
60 segment drives
HOST PROCESSOR/ MICROCONTROLLER
SDA SCL PCA9620
LCD PANEL (up to 480 elements)
8 backplanes
A0
A1
CLK n.c.
VSS
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VSS
VDD1 from 2.5 V to 5.5 V, VDD2 from 2.5 V to 5.5 V and VLCD from 2.5 V to 9.0 V.
Fig 5.
Typical system configuration when using an external VLCD
The host microprocessor or microcontroller maintains the 2 line I2C-bus communication channel with the PCA9620. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are the power supplies (VDD1, VDD2, VSS, VLCD), the external capacitors, and the LCD panel selected for the application. The minimum recommended values for external capacitors on VDD1, VDD2, and VLCD are nominal 100 nF. When using bigger capacitors, especially on the VLCD, the generated ripple will be consequently smaller, however it will take longer for the internal charge pump to first reach the target VLCD voltage. In the case that VDD1 and VDD2 are connected externally, the capacitors on VDD1 and VDD2 can be replaced by a single capacitor with a minimum value of 200 nF. Remark: In the case of insufficient decoupling, ripple of VDD1 and VDD2 will create additional VLCD ripple. The ripple on VLCD can be reduced by making the VSS connection as low-ohmic as possible. Excessive ripple on VLCD may give rise to flicker on the display.
7.3 Start-up and shut-down
7.3.1 Power-On Reset (POR)
At power-on the PCA9620 resets to starting conditions as follows: 1. All backplane outputs are set to VSS. 2. All segment outputs are set to VSS. 3. Selected drive mode is: 1:8 with 14 bias. 4. Input and output bank selectors are reset. 5. The I2C-bus interface is initialized. 6. The data pointer is cleared (set logic 0). 7. The Internal oscillator is running; no clock signal is available on pin CLK; pin CLK is in 3-state. 8. Temperature measurement is enabled.
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9. Temperature filter is disabled. 10. The internal VLCD voltage generation is disabled. The charge pump is switched off. 11. The VLCD temperature compensation is enabled. 12. The display is disabled. Remark: Do not transfer data on the I2C-bus for at least 1 ms after a power-on to allow the reset action to complete. The first command sent to the device after the power-on event must be the initialize command (see Section 7.1.1 on page 5). After Power-On Reset (POR) and before enabling the display, the RAM content should be brought to a defined status
* by clearing it (setting it all logic 0) or * by writing meaningful content (e.g. a graphic)
otherwise unwanted display artifacts may appear on the display.
Table 25. Reset states Bits labeled - are undefined at power-on. Command name initialize OTP-refresh oscillator-ctrl charge-pump-ctrl temp-msr-ctrl temp-comp-SLA temp-comp-SLB temp-comp-SLC temp-comp-SLD set-VPR-MSB set-VPR-LSB display-enable set-MUX-mode set-bias-mode load-data-pointer frame-frequency input-bank-select output-bank-select write-RAM-data temp-read invmode_CPF_ctrl temp-filter Bits 7 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 6 0 1 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 5 1 0 0 0 0 0 1 1 1 0 0 1 0 0 0 1 0 0 0 0 0 4 1 1 0 0 0 1 0 0 1 0 1 1 0 0 0 0 0 1 0 1 1 3 1 0 1 0 1 1 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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7.3.2 Recommended start-up sequences
This chapter describes how to proceed with the initialization of the chip in different application modes.
START
Set VPR register to desired VLCD value
Power-on VDD1 and VDD2 at the same time
Set multiplication factor for charge pump and enable it
Wait 1 ms Wait till VLCD reaches programmed value(1)
Initialize command
Initiate an OTP-refresh
Write RAM content to be displayed and enable the display(2)
STOP
013aaa249
(1) This time depends on the external capacitor on pin VLCD. For a capacitor of 100 nF a delay of 5 ms to 15 ms is expected. When using the internal VLCD generation, the display must not be enabled before the generation of VLCD with the internal charge pump is completed, otherwise unwanted display artifacts may appear on the display. (2) RAM data may be written before or during the ramp-up of VLCD.
Fig 6.
Recommended start-up sequence when using the internal charge pump and the internal clock signal
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START
Power-on VDD1, VDD2, and VLCD at the same time
Initiate an OTP-refresh
Wait 1 ms
Write RAM content to be displayed and enable the display
Initialize command
STOP
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Fig 7.
Recommended start-up sequence when using an external supplied VLCD and the internal clock signal
START
Power-on VDD1 and VDD2 at the same time
Apply external clock signal to pin CLK; set OSC bit logic 1(1)
Wait till VLCD reaches programmed value(2)
(1)
Wait 1 ms
Set VPR register to desired VLCD value
Initialize command Set multiplication factor for charge pump and enable it
Write RAM content to be displayed and enable the display(3)
STOP
Initiate an OTP-refresh
013aaa251
(1) The external clock signal can be applied after the generation of the VLCD voltage as well. (2) This time depends on the external capacitor on pin VLCD. For a capacitor of 100 nF a delay of 5 ms to 15 ms is expected. (3) RAM data may be written before or during the ramp-up of VLCD.
Fig 8.
Recommended start-up sequence when using the internal charge pump and an external clock signal
PCA9620
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START
Power-on VDD1, VDD2, and VLCD at the same time
Apply external clock signal to pin CLK; set OSC bit logic 1
Wait 1 ms Write RAM content to be displayed and enable the display
Initialize command
STOP Initiate an OTP-refresh
013aaa252
Fig 9.
Recommended start-up sequence when using an external supplied VLCD and an external clock signal
7.3.3 Recommended power-down sequences
With the following sequences the PCA9620 can be set to a state of minimum power consumption, called power-down mode.
START
Disable display by setting bit E logic 0
Stop generation of VLCD by setting bit CPE logic 0
Disable temperature measurement by setting bit TME logic 0
STOP
013aaa253
Fig 10. Recommended power-down sequence for minimum power-down current when using the internal charge pump and the internal clock signal
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START
Disable display by setting bit E logic 0
Disable temperature measurement by setting bit TME logic 0
STOP
013aaa254
Fig 11. Recommended power-down sequence when using an external supplied VLCD and the internal clock signal
START
Disable display by setting bit E logic 0
Stop generation of VLCD by setting bit CPE logic 0
Bring pin CLK to 3-state by setting bit OSC and bit COE logic 0
Disable temperature measurement by setting bit TME logic 0
External clock may be switched off
STOP
013aaa255
Fig 12. Recommended power-down sequence when using the internal charge pump and an external clock signal
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START Bring pin CLK to 3-state by setting bit OSC and bit COE logic 0
Disable display by setting bit E logic 0
Disable temperature measurement by setting bit TME logic 0
External clock may be switched off
STOP
013aaa256
Fig 13. Recommended power-down sequence when using an external supplied VLCD and an external clock signal
Remark: It is necessary to run the power-down sequence before removing the supplies. Depending on the application, care must be taken that no other signals are present at the chip input or output pins when removing the supplies (please refer to Section 9 on page 53). Otherwise this may cause unwanted display artifacts. In case of uncontrolled removal of supply voltages the PCA9620 will not be damaged. Remark: Static voltages across the liquid crystal display can build up when the external LCD supply voltage (VLCD) is on while the IC supply voltage (VDD1 or VDD2) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, external VLCD, VDD1, and VDD2 must be applied or removed together. Remark: A clock signal must always be supplied to the device when the device is active; removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal. It is recommended to first disable the display and afterwards to remove the clock signal.
7.4 LCD voltage
7.4.1 LCD voltage selector
The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the set-bias-mode command (see Table 14 on page 8) and the set-MUX-mode command (see Table 13 on page 8). Intermediate LCD biasing voltages are obtained from an internal voltage divider. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D), are given in Table 26. Discrimination is a term which is defined as the ratio of the on and off RMS voltage across a segment. It can be thought of as a measurement of contrast.
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Table 26. LCD drive mode static
LCD drive modes: summary of characteristics Number of: Backplanes Levels 1 2 2 2 4 4 4 6 6 6 8 8 8 2 3 4 5 3 4 5 3 4 5 3 4 5 LCD bias configuration static
1 1 1 1 1 1 1 1 1 1 1 1 2 3 4 2 3 4 2 3 4 2 3 4
V off ( RMS ) ---------------------V LCD 0 0.354 0.333 0.395 0.433 0.333 0.331 0.456 0.333 0.306 0.467 0.333 0.293
V on ( RMS ) ---------------------V LCD 1 0.791 0.745 0.729 0.661 0.577 0.545 0.612 0.509 0.467 0.586 0.471 0.424
VLCD[2] V on ( RMS ) D = ---------------------- [1] V off ( RMS )
2.236 2.236 1.845 1.527 1.732 1.646 1.341 1.527 1.527 1.254 1.414 1.447
Von(RMS) 2.828 x Voff(RMS) 3.0 x Voff(RMS) 2.529 x Voff(RMS) 2.309 x Voff(RMS) 3.0 x Voff(RMS) 3.024 x Voff(RMS) 2.191 x Voff(RMS) 3.0 x Voff(RMS) 3.266 x Voff(RMS) 2.138 x Voff(RMS) 3.0 x Voff(RMS) 3.411 x Voff(RMS)
1:2 multiplex 1:2 multiplex 1:2 1:4 1:4 1:6 multiplex[3] multiplex[3] multiplex[3] multiplex[3]
1:4 multiplex
1:6 multiplex 1:6 multiplex 1:8 1:8 multiplex[3] multiplex[3]
1:8 multiplex
[1] [2] [3]
Determined from Equation 3. Determined from Equation 2. In this examples the discrimination factor and hence the contrast ratios are smaller. The advantage of these LCD drive modes is a power saving from a reduction of the LCD voltage VLCD.
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In the static drive mode a suitable choice is VLCD > 3Vth. 1 Bias is calculated by ------------ , where the values for a are 1+a a = 1 for 12 bias a = 2 for 13 bias a = 3 for 14 bias The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1: V on ( RMS ) = a 2 + 2a + n ----------------------------2 n x (1 + a) (1)
V LCD
where VLCD is the resultant voltage at the LCD segment and where the values for n are n = 1 for static mode n = 2 for 1:2 multiplex n = 4 for 1:4 multiplex n = 6 for 1:6 multiplex n = 8 for 1:8 multiplex The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:
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V off ( RMS ) =
V LCD
a 2 - 2a + n ----------------------------2 n x (1 + a)
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3: V on ( RMS ---------------------) = V off ( RMS ) (a + 1) + (n - 1) ------------------------------------------2 (a - 1) + (n - 1)
2
(3)
It should be noted that VLCD is sometimes referred as the LCD operating voltage. 7.4.1.1 Electro-optical performance Suitable values for Von(RMS) and Voff(RMS) are dependant on the LCD liquid used. The RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of the pixel. For any given liquid, there are two threshold values defined. One point is at 10 % relative transmission (at Vlow) and the other at 90 % relative transmission (at Vhigh), see Figure 14. For a good contrast performance, the following rules should be followed: V on ( RMS ) V high V off ( RMS ) V low (4) (5)
Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection of a, n (see Equation 1 to Equation 3) and the VLCD voltage. Vlow and Vhigh are properties of the LCD liquid and can be provided by the module manufacturer. It is important to match the module properties to those of the driver in order to achieve optimum performance.
100 % 90 % Relative Transmission 10 % Vlow OFF SEGMENT Vhigh VRMS [V] ON SEGMENT
001aam358
GREY SEGMENT
Fig 14. Electro-optical characteristic: relative transmission curve of the liquid
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7.4.2 LCD drive mode waveforms
7.4.2.1 Static drive mode The static LCD drive mode is used when a single backplane is provided in the LCD.
Tfr
VLCD BP0 VSS VLCD Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD
LCD segments
state 1 (on)
state 2 (off)
state 1
0V
-VLCD
VLCD
state 2
0V
-VLCD (b) Resultant waveforms at LCD segment.
013aaa207
Vstate1(t) = VSn(t) - VBP0(t). Vstate2(t) = V(Sn + 1)(t) - VBP0(t). Von(RMS)(t) = VLCD. Voff(RMS)(t) = 0 V.
Fig 15. Static drive mode waveforms (line inversion mode)
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7.4.2.2
1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCA9620 allows the use of 12 bias or 13 bias in this mode as shown in Figure 16 and Figure 17.
Tfr VLCD BP0 VLCD/2 VSS state 1 VLCD BP1 VLCD/2 VSS VLCD Sn VSS VLCD Sn+1 VSS (a) Waveforms at driver. VLCD VLCD/2 state 1 0V
-VLCD/2 -VLCD
LCD segments
state 2
VLCD VLCD/2 state 2 0V
-VLCD/2 -VLCD
(b) Resultant waveforms at LCD segment.
013aaa208
Vstate1(t) = VSn(t) - VBP0(t). Vstate2(t) = VSn(t) - VBP1(t). Von(RMS)(t) = 0.791VLCD. Voff(RMS)(t) = 0.354VLCD.
Fig 16. Waveforms for the 1:2 multiplex drive mode with 12 bias (line inversion mode)
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Tfr
BP0
VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3
LCD segments
state 1 state 2
BP1
Sn
Sn+1
state 1
0V -VLCD/3 -2VLCD/3 -VLCD VLCD 2VLCD/3 VLCD/3
state 2
0V -VLCD/3 -2VLCD/3 -VLCD (b) Resultant waveforms at LCD segment.
013aaa209
Vstate1(t) = VSn(t) - VBP0(t). Vstate2(t) = VSn(t) - VBP1(t). Von(RMS)(t) = 0.745VLCD. Voff(RMS)(t) = 0.333VLCD.
Fig 17. Waveforms for the 1:2 multiplex drive mode with 13 bias (line inversion mode)
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7.4.2.3
1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as shown in Figure 18.
Tfr VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 0V -VLCD/3 -2VLCD/3 -VLCD VLCD 2VLCD/3 VLCD/3 0V -VLCD/3 -2VLCD/3 -VLCD state 1 state 2 LCD segments
BP0
BP1
BP2
BP3
Sn
Sn+1
Sn+2
Sn+3
state 1
state 2
(b) Resultant waveforms at LCD segment.
013aaa211
Vstate1(t) = VSn(t) - VBP0(t). Vstate2(t) = VSn(t) - VBP1(t). Von(RMS)(t) = 0.577VLCD. Voff(RMS)(t) = 0.333VLCD.
Fig 18. Waveforms for the 1:4 multiplex drive mode with 13 bias (line inversion mode)
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7.4.2.4
1:6 Multiplex drive mode When six backplanes are provided in the LCD, the 1:6 multiplex drive mode applies. The PCA9620 allows the use of 13 bias or 14 bias in this mode as shown in Figure 19 and Figure 20.
Tfr VLCD 2VLCD / 3 VLCD / 3 VSS state 1
LCD segments state 2
BP0
BP1
VLCD 2VLCD / 3 VLCD / 3 VSS
BP2
VLCD 2VLCD / 3 VLCD / 3 VSS
BP3
VLCD 2VLCD / 3 VLCD / 3 VSS
BP4
VLCD 2VLCD / 3 VLCD / 3 VSS
BP5
VLCD 2VLCD / 3 VLCD / 3 VSS
Sn
VLCD 2VLCD / 3 VLCD / 3 VSS
Sn + 1
VLCD 2VLCD / 3 VLCD / 3 VSS
VLCD 2VLCD / 3 state 1 VLCD / 3 VSS -VLCD / 3 -2VLCD / 3 -VLCD VLCD 2VLCD / 3 VLCD / 3 VSS -VLCD / 3 -2VLCD / 3 -VLCD
state 2
001aal399
Vstate1(t) = VSn(t) - VBP0(t). Vstate2(t) = VSn(t) - VBP1(t). Von(RMS)(t) = 0.509VLCD. Voff(RMS)(t) = 0.333VLCD.
Fig 19. Waveforms for 1:6 multiplex drive mode with 13 bias (line inversion mode)
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Universal LCD driver for low multiplex rates
Tfr VLCD 3VLCD / 4 BP0 VLCD / 4 VSS VLCD 3VLCD / 4 BP1 VLCD / 4 VSS VLCD 3VLCD / 4 BP2 VLCD / 4 VSS VLCD 3VLCD / 4 BP3 VLCD / 4 VSS VLCD 3VLCD / 4 BP4 VLCD / 4 VSS VLCD 3VLCD / 4 BP5 VLCD / 4 VSS VLCD Sn VLCD / 2 VSS VLCD Sn + 1 VLCD / 2 VSS VLCD 3VLCD / 4 VLCD / 4 VSS -VLCD / 4 -3VLCD / 4 -VLCD VLCD 3VLCD / 4 VLCD / 2 VLCD / 4 VSS state 2 -VLCD / 4 -VLCD / 2 -3VLCD / 4 -VLCD LCD segments state 1 state 2
state 1
001aal400
Vstate1(t) = VSn(t) - VBP0(t). Vstate2(t) = VSn(t) - VBP1(t). Von(RMS)(t) = 0.467VLCD. Voff(RMS)(t) = 0.306VLCD.
Fig 20. Waveforms for 1:6 multiplex drive mode with 14 bias (line inversion mode)
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7.4.2.5
1:8 Multiplex drive mode
Tfr VLCD 3VLCD / 4 BP0 VLCD / 4 VSS VLCD 3VLCD / 4 BP1 VLCD / 4 VSS VLCD 3VLCD / 4 BP2 VLCD / 4 VSS VLCD 3VLCD / 4 BP3 VLCD / 4 VSS VLCD 3VLCD / 4 BP4 3LCD / 4 VSS VLCD 3VLCD / 4 BP5 VLCD / 4 VSS VLCD 3VLCD / 4 BP6 VLCD / 4 VSS VLCD 3VLCD / 4 BP7 VLCD / 4 VSS VLCD Sn VLCD / 2 VSS VLCD Sn + 1 VLCD / 2 VSS VLCD 3VLCD / 4 VLCD / 4 VSS -VLCD / 4 -3VLCD / 4 -VLCD VLCD 3VLCD / 4 VLCD / 2 VLCD / 4 VSS -VLCD / 4 -VLCD / 2 -3VLCD / 4 -VLCD LCD segments state 1 state 2
state 1
state 2
001aal398
Vstate1(t) = VSn(t) - VBP0(t). Vstate2(t) = VSn(t) - VBP1(t). Von(RMS)(t) = 0.424VLCD. Voff(RMS)(t) = 0.293VLCD.
Fig 21. Waveforms for 1:8 multiplex drive mode with 14 bias (line inversion mode)
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VLCD 3/4 VLCD BP0 1/4 VLCD VSS VLCD 3/4 VLCD BP1 1/4 VLCD VSS VLCD 3/4 VLCD BP2 1/4 VLCD VSS VLCD 3/4 VLCD BP3 1/4 VLCD VSS VLCD 3/4 VLCD BP4 1/4 VLCD VSS VLCD 3/4 VLCD BP5 1/4 VLCD VSS VLCD 3/4 VLCD BP6 1/4 VLCD VSS VLCD 3/4 VLCD BP7 1/4 VLCD VSS VLCD Sn 1/2 VLCD VSS VLCD Sn + 1 1/2 VLCD VSS VLCD 3/4 VLCD 1/2 VLCD 1/4 VLCD VSS 1/4 VLCD 1/2 VLCD 3/4 VLCD VLCD VLCD 3/4 VLCD 1/2 VLCD 1/4 VLCD VSS 1/4 VLCD 1/2 VLCD 3/4 VLCD VLCD
Tfr frame n
Tfr frame n+1 state 1
LCD segments state 2
state 1
state 2
001aam359
Vstate1(t) = VSn(t) - VBP0(t). Vstate2(t) = VSn(t) - VBP1(t). Von(RMS)(t) = 0.424VLCD. Voff(RMS)(t) = 0.293VLCD.
Fig 22. Waveforms for 1:8 multiplex drive mode with 14 bias (frame inversion mode)
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When eight backplanes are provided in the LCD, the 1:8 multiplex drive mode applies, as shown in Figure 21 and Figure 22.
7.4.3 VLCD generation
VLCD can be generated and controlled on the chip by using software commands. When the internal charge pump is used, the programmed VLCD is available on pin VLCD. The charge pump generates a VLCD of up to 3 x VDD2. The charge pump can be enabled or disabled with the CPE bit (see Table 8 on page 7). With bit CPC the charge pump multiplier setting can be configured. The final value of VLCD is a combination of the programmed VPR[7:0] value and the output of the temperature compensation block, VT[7:0]. The system is shown in Figure 23.
SLA
SLB
SLC
SLD
0 OFFSET TEMPERATURE READOUT
8 8
TD -40 0 +20 +50 +80 TEMPERATURE n m
VPR[7:0]
8
VLCD
013aaa257
Fig 23. VLCD generation including temperature compensation
In Equation 6 the main parameters are the programmed digital value term and the compensated temperature term. V LCD = [ VPR [ 7:0 ] + VT [ 7:0 ] ] x n + m 1. VPR[7:0] is the binary value of the programmed voltage. 2. VT[7:0] is the binary value of the temperature compensated voltage. Its value comes from the temperature compensation block and is a two's complement which has the value 0h at 20 C. 3. m and n are fixed values (see Table 27).
Table 27. Symbol m n Parameters of VLCD generation Value 3 0.03 Unit V V
(6)
Figure 24 shows how VLCD changes with the programmed value of VPR[7:0].
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It has to be taken into account that the charge pump has to be configured (via bit CPC) properly to obtain the desired voltage range. For example, if VDD2 = 3.0 V and CPC is set to 2 x VDD2 (logic 0) then the maximum theoretical value that the charge pump can reach is VLCD = 6.0 V. But in reality, lower values will be reached due to internal resistances, see Section 7.4.5. So, if the requested value for VLCD = 7.0 V then the charge pump has to be configured with CPC set to 3 x VDD2 (logic 1).
V LCD
9V
(2)
n
VDD2
(1)
m
00
01
02
03
04
05
06
........................
C7
C8
C9 CA
...
FC
FD
FE
FF
VPR[7:0]
013aaa258
(1) If VDD2 > 3.0 V then VPR[7:0] must be set so that VLCD > VDD2. (2) Automatic limitation for VLCD > 9.0 V.
Fig 24. VLCD programming of PCA9620 (assuming VT[7:0] = 0h)
Programmable range of VPR[7:0] is from 0h to FFh. This would allow to achieve VLCD > 9.0 V, but the PCA9620 has a built-in automatic limitation of VLCD at 9.0 V. In case that VDD2 is higher than 3.0 V, then it is important that VPR[7:0] is set to a value such that the resultant VLCD (including the temperature correction of VT[7:0]) is higher than VDD2.
7.4.4 External VLCD supply
VLCD can be directly supplied to the VLCD pin. In this case the internal charge pump must not be enabled otherwise a high current may occur on pin VDD2 and pin VLCD. When VLCD is supplied externally, no internal temperature compensation occurs on this voltage even if bit TCE is set logic 1 (see Section 7.4.8 on page 36). The VLCD voltage which is supplied externally will be available at the segments and backplanes of the device through the chosen bias system. Also programming the VPR[7:0] bit field has no effect on the VLCD which is externally supplied.
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7.4.5 Charge pump driving capability
Figure 25 illustrates the main factor determining how much current the charge pump can deliver.
Regulated desired VLCD This supplies the segments and backplanes Theoretical VLCD value VLCD = 2 x VDD2 or VLCD = 3 x VDD2
Output Resistance Ro(cp)
013aaa259
Fig 25. Charge pump model (used to characterize the driving strength)
The output resistance of the charge pump is specified in Table 35 on page 55. With these values it can be calculated how much current the charge pump can drive under certain conditions. Example: Assuming the user would like to have the normal operation point at 25 C with VLCD = 7.0 V and VDD2 = 5.0 V and the charge pump is set to 2 x VDD2. Then the theoretical value of VLCD is 10.0 V and the desired one is 7.0 V. The difference between the theoretical maximum value and desired one is 3.0 V. The charge pump resistance is nominally 0.85 k. Equation 7 shows the possible current that the charge pump could deliver: I load = V LCD R o ( cp ) For this example we get: I load = 3.0 V 0.85 k = 3.5 mA In cases where no extreme driving capability is needed, a command is available for decreasing the charge pump frequency (see Table 22 on page 11) and thus reducing the total current consumption. If the charge pump frequency is halved, then the driving capability is halved as well, whereas the output resistance doubles. (7)
7.4.6 Charge pump frequency settings and power efficiency
The PCA9620 offers the possibility to use different frequency settings for the charge pump. Bit CPF controls the frequency at which the charge pump is running (see Table 22 on page 11). This frequency has a direct influence on the current consumption of the IC but also on the charge pump driving capability. Using a lower charge pump frequency decreases the current consumption and the driving capability. The power efficiency of the charge pump determines in certain applications which frequency settings to choose for the CPF bit. In the example shown in Figure 26, the current consumption was measured with the charge pump set to 2 x VDD2 and with VDD2 = 3.0 V and VPR[7:0] set to maximum to obtain the maximum possible VLCD with this setup, which is close to 6.0 V. The current load on pin VLCD determines the output power delivered by the IC: P o = I load x V LCD The current consumption on pin VDD2 determines the input power taken by the IC:
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(8)
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PCA9620
Universal LCD driver for low multiplex rates (9)
P i = I DD2 x V DD2 The ratio between these two numbers determines the charge pump power efficiency: p = Po Pi
(10)
90 p (%) 70
(3) (4) (1) (2)
001aan027
7 VLCD (V) 5
50
3
30 0 200 400 600 800 Iload (A)
1 1000
Charge pump set to 2 x VDD2; VDD2 = 3 V. (1) p, full charge pump frequency. (2) p, half charge pump frequency. (3) VLCD, full frequency. (4) VLCD, half frequency.
Fig 26. Power efficiency of the charge pump
Loading the charge pump with higher currents decreases the output voltage. This decrease is determined by the charge pump driving capability, respectively by the output resistance of the charge pump (see Table 35 on page 55). The power efficiency calculation is only valid when the charge pump is running at its maximum peak frequency and regulates the generated VLCD voltage with full speed. In this case, the ripple on the VLCD voltage equals the internal charge pump frequency. Approximately, this could also be calculated with the parameter of the output resistance of the charge pump (see Table 35 on page 55), the load current, and the voltage needed to be provided by using Equation 7 on page 33. This value of Iload is close to the value of the load current needed for the application. If the application runs with VDD2 = 3.0 V, the load currents are up to 400 A (DC measured), and the VLCD generated voltages are up to 5.0 V, then - concerning power efficiency - it would be the best to have a charge pump frequency set to half frequency.
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In case it is desired to change the charge pump frequency, it is recommended to make a graph like Figure 26 and understand what the application requirements are. This would basically imply to find out what would be the maximum VLCD requirements and what would be the maximum load currents required. Then it can be decided which is the best setting of bit CPF. Tuning the charge pump frequency might be a difficult task to do and requires good knowledge of the application in which the IC is being used; therefore, NXP recommends to keep the CPF bit set logic 0 to have the maximum charge pump frequency, thus having the maximum driving strength.
7.4.7 Temperature readout
The PCA9620 has a built-in temperature sensor which provides a 8 bit digital value, TD[7:0], of the ambient temperature. This value can be read through the I2C interface (see Figure 49 on page 52). The actual temperature is determined from TD[7:0] using Equation 11: T (C) = 0.9375 x TD [ 7:0 ] - 40 (11)
The measurement needs about 5 ms to complete and is repeated periodically as soon as bit TME is set logic 1 (see Table 9 on page 7). The time between measurements is linked to the system clock and hence varies with changes in the chosen frame frequency, see Table 28.
Table 28. 60 Hz 200 Hz 300 Hz Temperature measurement update rate Temperature measurement update rate 3.3 s 1s 0.67 s
Selected frame frequency
Due to the nature of a temperature sensor, oscillations on the VLCD may occur. To avoid this, a filter has been implemented in PCA9620. The system is shown in Figure 27.
TEMPERATURE MEASUREMENT BLOCK
TD[7:0] unfiltered
DIGITAL TEMPERATURE FILTER
TD[7:0] filtered
To the readout register via I2C-bus and to the VLCD compensation block
enabled or disabled by bit TFE
013aaa260
Fig 27. Temperature measurement block with digital temperature filter
Like any other filtering, the digital temperature filter (see Figure 27) introduces a certain delay in the measurement of temperature. This behavior is illustrated in Figure 28.
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50 T (C) 40
001aal393
16 T (C)(3) 12
30
(1) (2)
8
20
4
10
(3)
0
0 0 40 80 120 t (s)
-4 160
(1) Environment temperature, T1 (C). (2) Measured temperature, T2 (C). (3) Temperature deviation, T = T2 - T1.
Fig 28. Temperature measurement delay
This delay may cause undesired effects at start-up when the environment temperature may be different than the reset value of the PCA9620 which is 20 C. In this case it takes up to 30 s till the correct measured temperature value will be available. A control bit, TFE, is implemented to enable or disable the digital temperature filter. This bit is set logic 0 by default which means that the filter is disabled and the unfiltered environment temperature value is available to calculate the desired VLCD.
7.4.8 Temperature compensation of VLCD
Due to the temperature dependency of the liquid crystal viscosity the LCD controlling voltage VLCD might have to be adjusted at different temperatures to maintain optimal contrast. The temperature behavior of the liquid comes from the LCD manufacturer. The slope has to be set to compensate for the liquid behavior. Internal temperature compensation may be enabled via bit TCE. The ambient temperature range is split up into four equally sized regions and a different temperature coefficient can be applied to each (see Figure 29). Each coefficient can be selected from a choice of eight different slopes. Each one of these coefficients (see Table 29) may be independently selected via the temp-comp-SLA to temp-comp-SLD commands (see Table 4 on page 5).
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Temperature coefficients Corresponding slope factor (mV/C) 0 -4 -8 -16 -40 +4 +8 +16 Temperature coefficients MA, MB, MC, MD[1] 0.00 -0.125 -0.25 -0.5 -1.25 0.125 0.25 0.5
Table 29.
SLA[2:0] to SLD[2:0] value 000[2] 001 010 011 100 101 110 111
[1]
The relationship between the temperature coefficients MA to MD and the slope factor is derived from the
following equation: Mx = --------------- x ------------- .
[2] Default value.
0.9375 0.03
slope 1000
The slope factors imply a linear correction, however the implementation is set in steps of 30 mV (parameter n in Table 27 on page 31).
SLA
SLB
SLC
SLD
TD[7:0] 0h 20h 40h 60h 7Fh
VLCD with temperature compensation (V)
zero offset at 20 C
MA
MB
MC
MD
-40
-10
20
50
79 Temperature (C)
013aaa261
Fig 29. Example of segmented temperature coefficients
Remark: After reset, VLCD is fixed because the VPR[7:0] bit field is reset logic 0. The value of VT[7:0] is generated by the reset value of TD[7:0] (40h, representing 20 C). Temperature compensation is implemented by adding an offset VT[7:0] to the VPR[7:0] value. VT[7:0] is a two's complement number that equals 0h at 20 C. The final result for VLCD calculation is an 8-bit positive number (see Equation 6 on page 31). Remark: Care must be taken that the ranges of VPR[7:0] and VT[7:0] don't cause clipping and hence undesired results. The device will not permit overflow or underflow and will clamp results to either end of the range.
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The Voffset(LCD) value can be calculated with the equations given in Table 30: V offset ( LCD ) = m x V T
Table 30. T -40 C -40 C T -10 C -10 C < T 20 C 20 C < T 50 C 50 C < T < 80 C 80 C T
[1]
(12)
Calculation of the temperature compensated voltage VT TD[7:0] 0h 0h to 20h 21h to 40h 41h to 60h 61h to 7Eh 7Fh[1] Offset equation for VT V T = - 32 x MA - 32 x MB V T = ( TD [ 7:0 ] - 32 ) x MA - 32 x MB V T = ( TD [ 7:0 ] ( - 64 ) ) x MB V T = ( TD [ 7:0 ] - 64 ) x MC V T = ( TD [ 7:0 ] - 96 ) x MD + 32 x MC V T = 31 x MD + 32 x MC
Temperature range
No temperature compensation is possible above 80 C. Above this value, the system maintains the compensation value from 80 C.
Example: Assumed that Tamb = -8 C; TD[7:0] = 22h; MB = -0.5: V offset ( LCD ) = m x V T = m x ( TD[7:0] - 64 ) x MB = 30mV x ( ( 34 - 64 ) x - 0.5 ) = 30mV x - 30 x - 0.5 = 450mV The VT[7:0] term is calculated using the digital temperature value TD[7:0] which is provided by the temperature measurement block (Section 7.4.7). Therefore the accuracy of the temperature measurement block (Tacc, see Table 35 on page 55) will be directly translated to the LCD voltage deviation VLCD. Since VT[7:0] = f[T,slope] and Tacc = 6 C then V T = T acc x slope , where slope has one of the possible values specified in Table 29. This term will be added to the total LCD voltage deviation Voffset(LCD)tot over the temperature range. So the total VLCD offset will be: V offset ( LCD )tot = V LCD + V T .
7.5 Oscillator
The internal logic and LCD drive signals of the PCA9620 are timed by a frequency fclk which either is the built-in oscillator frequency fosc or equals an external clock frequency.
7.5.1 Internal oscillator
When the internal oscillator is used, it is possible to make the clock signal available on pin CLK by using the oscillator-ctrl command (see Table 7 on page 6). If this is not intended, pin CLK should be left open. At power-on the signal at pin CLK is disabled and pin CLK is in 3-state. The duty cycle of the output clock provided on the CLK pin is not always 50 : 50. Table 17 on page 9 shows the expected duty cycle for each of the chosen frame frequencies.
7.5.2 External clock
In applications where an external clock needs to be applied to the PCA9620, bit OSC (see Table 7 on page 6) must be set logic 1. In this case pin CLK becomes an input. The CLK signal is a signal that is fed into the VDD1 domain so it must have an amplitude equal to the VDD1 voltage supplied to the chip and be referenced to VSS. The clock frequency (fclk) determines the LCD frame frequency ffr.
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Remark: In case that a external clock is used then this clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal. Removal of the clock is possible when following the correct procedures. See Figure 12 on page 19 and Figure 13 on page 20.
7.5.3 Timing and frame frequency
The timing of the PCA9620 organizes the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. The timing also generates the LCD frame frequency which it derives as an integer division of the clock frequency. The frame frequency is a fixed division of the internal clock or of the frequency applied to pin CLK when an external clock is used: f clk f fr = ------48 (13)
When the internal clock is used, the clock and frame frequency can be programmed by software such that the nominal frame frequency can be chosen in steps of 10 Hz in the range of 60 Hz to 300 Hz (see Table 17 on page 9). Furthermore the nominal frame frequency is factory-calibrated with an accuracy of 15 %. When the internal clock is enabled at pin CLK by using bit COE, the duty ratio of the clock may change when choosing different values for the frame frequency prescaler. Table 17 on page 9 shows the different output duty ratios for each frame frequency prescaler setting.
7.6 Backplane outputs
The LCD drive section includes eight backplane outputs: BP0 to BP7. The backplane output signals are generated based on the selected LCD multiplex drive mode. Table 31 describes which outputs are active for each of the multiplex drive modes and what signal is generated.
Table 31. Multiplex drive mode 1:8 1:6 1:4 1:2 static
[1]
Mapping of output pins and corresponding output signals with respect to the multiplex driving mode Output pin BP0 Signal BP0 BP0 BP0 BP0 BP0 BP1 BP1 BP1 BP1 BP0[1] BP2 BP2 BP2 BP0[1] BP0[1] BP3 BP3 BP3 BP1[1] BP0[1] BP4 BP4 BP0[1] BP0[1] BP0[1] BP5 BP5 BP1[1] BP1[1] BP0[1] BP6 BP0[1] BP2[1] BP0[1] BP0[1] BP7 BP1[1] BP3[1] BP1[1] BP0[1] BP1 BP2 BP3 BP4 BP5 BP6 BP7
These pins may optionally be connected to the display to improve drive strength. Connect only with the corresponding output pin carrying the same signal. If not required they can be left open-circuit.
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7.7 Segment outputs
The LCD drive section includes 60 segment outputs (S0 to S59) which must be connected directly to the LCD. The segment output signals are generated based on the multiplexed backplane signals and with data resident in the display register. When less than 60 segment outputs are required, the unused segment outputs must be left open-circuit.
7.8 Display register
The display register holds the display data while the corresponding multiplex signals are generated.
7.9 Display RAM
The display RAM is a static 60 x 8-bit RAM which stores LCD data. Logic 1 in the RAM bit map indicates the on-state of the corresponding LCD element; similarly, logic 0 indicates the off-state. There is a one-to-one correspondence between
* the bits in the RAM bitmap and the LCD elements * the RAM columns and the segment outputs * the RAM rows and the backplane outputs.
The display RAM bit map, Figure 30, shows row 0 to row 7 which correspond with the backplane outputs BP0 to BP7, and column 0 to column 59 which correspond with the segment outputs S0 to S59. In multiplexed LCD applications the data of each row of the display RAM is time-multiplexed with the corresponding backplane (row 0 with BP0, row 1 with BP1 and so on). When display data is transmitted to the PCA9620 the display bytes received are stored in the display RAM in accordance with the selected LCD multiplex drive mode. The data is stored as it arrives and does not wait for the acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, quadruples, sextuples or bytes.
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columns display RAM columns/segment outputs (S) static drive mode 0 1 2 3 4 5 6 7 0 1 2 3 4 55 56 57 58 59 bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7
multiplex 1:2 drive mode 0 1 rows display RAM rows/ backplane outputs (BP) 2
0
1
2
3
4
55
56 57 58 59 bank 0
bank 2 3 4 bank 4 5 6 7 bank 6
multiplex 1:4 drive mode 0 1
0
1
2
3
4
55
56 57 58 59
bank 0 2 3 4 5 6 7
013aaa262
bank 4
The display RAM bitmap shows the direct relationship between the display RAM column and the segment outputs, between the bits in a RAM row and the backplane outputs, and between the RAM rows and banks.
Fig 30. Display RAM bitmap
7.9.1 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load-data-pointer command. Following this command, an arriving data byte is stored starting at the display RAM address indicated by the data pointer.
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The data pointer is automatically incremented in accordance with the chosen LCD multiplex drive mode configuration. That is, after each byte is stored, the contents of the data pointer are incremented
* * * * *
by eight (static drive mode) by four (1:2 multiplex drive mode) by two (1:4 multiplex drive mode) by one or two (1:6 multiplex drive mode), see Figure 37 on page 45 by one (1:8 multiplex drive mode)
If the data pointer reaches the end of the RAM row it is automatically wrapped around to address 0. This means that it can be continuously written to or read from the display RAM. The data pointer should always be set to an address where the remaining RAM is divisible by eight because odd bits will be discarded (see Figure 32). This behavior is actually only shown in static drive mode because of the fact that the 60 RAM cells can't be divided by eight without remainder. If an I2C-bus data access is terminated early then the state of the data pointer is unknown. The data pointer must then be re-written prior to further RAM accesses. 7.9.1.1 RAM filling in static drive mode In the static drive mode the eight transmitted data bits are placed in eight successive display RAM columns in row 0 (see Figure 31).
columns display RAM columns/segment outputs (S) rows 0 1 2 3 4 5 6 7 55 56 57 58 59
display RAM rows/ 0 b7 b6 b5 b4 b3 b2 b1 b0 backplane outputs (BP)
b7 b6 b5 b4 b3 b2 b1 b0 MSB transmitted data byte
013aaa263
LSB
Fig 31. Display RAM filling order in static drive mode
In order to fill the whole RAM row, 8 bytes must be sent to the PCA9620, but the last 4 bits from the last byte are discarded, and the data pointer is wrapped around to column 0 to start a possible RAM content update (see Figure 32).
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data pointer
0
1
2
3
4
5
6
7
48 49 50 51 52 53 54 55 56 57 58 59 f7 f6 f5 f4 f3 f2 f1 f0 g7 g6 g5 g4 g3 g2 g1 g0 discarded wrap around
0 a7 a6 a5 a4 a3 a2 a1 a0 display RAM
013aaa287
Fig 32. Discarded bits and data pointer wrap around at the end of data transmission
7.9.1.2
RAM filling in 1:2 multiplex drive mode In the 1:2 multiplex drive mode the eight transmitted data bits are placed in four successive display RAM columns of two rows (see Figure 33).
columns display RAM columns/segment outputs (S) rows 0 1 2 3 4 5 6 7 55 56 57 58 59 LSB b7 b6 b5 b4 b3 b2 b1 b0 MSB transmitted data byte
013aaa264
display RAM rows/ 0 b7 b5 b3 b1 backplane outputs 1 b6 b4 b2 b0 (BP)
Fig 33. Display RAM filling order in 1:2 multiplex drive mode
In order to fill the whole two RAM rows 15 bytes need to be sent to the PCA9620. After the last byte sent the data pointer is wrapped around to column 0 to start a possible RAM content update (see Figure 34). Even if a data byte is transmitted during the wrapping of the data pointer, then all the bits in the byte will be written correctly.
data pointer
0
1
2
3
4
5
6
7
55 56 57 58 59 b7 b5 b3 b6 b4 b2
0 b1 display RAM 1 b0
wrap around
013aaa288
Fig 34. Data pointer wrap around in 1:2 multiplex drive mode
7.9.1.3
RAM filling in 1:4 multiplex drive mode In the 1:4 multiplex drive mode the eight transmitted data bits are placed in two successive display RAM columns of four rows (see Figure 35).
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columns display RAM columns/segment outputs (S) 012 0 b7 b3 1 b6 b2 2 b5 b1 display RAM rows/ backplane outputs (BP) 3 b4 b0 3 4 5 6 7 55 56 57 58 59
rows
b7 b6 b5 b4 b3 b2 b1 b0 MSB transmitted data byte
013aaa265
LSB
Fig 35. Display RAM filling order in 1:4 multiplex drive mode
In order to fill the whole four RAM rows 30 bytes need to be sent to the PCA9620. After the last byte sent, the data pointer is wrapped around to column 0 to start a possible RAM content update (see Figure 36). Even if a data byte is transmitted during the wrapping of the data pointer, all the bits in the byte will be written correctly.
columns display RAM columns/segment outputs (S) data pointer 01 0 b3 1 b2 2 b1 3 b0 2 3 4 5 6 7 55 56 57 58 59 b7 b6 b5 b4
display RAM
wrap around
013aaa289
Fig 36. Data pointer wrap around in 1:4 multiplex drive mode
7.9.1.4
RAM filling in 1:6 multiplex drive mode In the 1:6 multiplex drive mode the RAM is organized in six rows and 60 columns. The eight transmitted data bits are placed in such a way, that a column is filled up (see Figure 37).
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data pointer incrementation 0 1 2 3
columns display RAM columns/segment outputs (S)
4
5
6
7
55 56 57 58 59
0 a7 a1 b3 c5 rows display RAM rows/ backplane outputs (BP) 1 a6 a0 b2 c4 2 a5 b7 b1 c3 3 a4 b6 b0 c2 4 a3 b5 c7 c1 5 a2 b4 c6 c0
MSB
LSB
a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0 c7 c6 c5 c4 c3 c2 c1 c0
transmitted data bytes
013aaa266
Fig 37. Display RAM filling order in 1:6 multiplex drive mode
The remaining bits are wrapped up into the next column. In order to fill the whole RAM addresses 45 bytes need to be sent to the PCA9620. After the last byte sent the data pointer is wrapped around to column 0 to start a possible RAM content update (see Figure 38). Even if a data byte is transmitted during the wrapping of the data pointer, all the bits in the byte will be written correctly.
data pointer
0
1
2
3
4
5
6
7
55 56 57 58 59 a7 a1 a6 a0 a5 b7 a4 b6 a3 b5 a2 b4
0 b3 c5 1 b2 c4 display RAM 2 b1 c3 3 b0 c2 4 c7 c1 5 c6 c0 wrap around
013aaa290
Fig 38. Data pointer wrap around in 1:6 multiplex drive mode
7.9.1.5
RAM filling in 1:8 multiplex drive mode In the 1:8 multiplex drive mode the eight transmitted data bits are placed into eight rows of one display RAM column (see Figure 39).
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columns display RAM columns/segment outputs (S) MSB
transmitted data byte LSB
b7 b6 b5 b4 b3 b2 b1 b0 0 0 b7 1 b6 rows display RAM rows/ backplane outputs (BP) 2 b5 3 b4 4 b3 5 b2 6 b1 7 b0
013aaa267
1
2
3
4
5
6
7
55 56 57 58 59
Fig 39. Display RAM filling order in 1:8 multiplex drive mode
In order to fill the whole RAM addresses 60 bytes need to be sent to the PCA9620. After the last byte sent the data pointer is wrapped around to column 0 to start a possible RAM content update (see Figure 40). In this case there is no situation possible where a transmitted data byte can be written over the RAM boundary.
data pointer
0 0 b7 1 b6 2 b5 3 b4 4 b3 5 b2 6 b1 7 b0
1
2
3
4
5
6
7
55 56 57 58 59 a7 a6 a5 a4 a3 a2 a1 a0
display RAM
wrap around
013aaa291
Fig 40. Data pointer wrap around in 1:8 multiplex drive mode
7.9.2 Bank selection
A RAM bank can be thought of as a collection of RAM rows. The PCA9620 includes a RAM bank switching feature in the static, 1:2, and 1:4 multiplex drive modes. The RAM bank switching gives the provision for preparing display information in an alternative bank and to be able to switch to it once it is complete. Input and output banks can be set independently from one another with the input-bank-select and the output-bank-select commands; Figure 41 shows the concept.
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INPUT-BANK-SELECT COMMAND CONTROLS THE INPUT DATA PATH
OUTPUT-BANK-SELECT COMMAND CONTROLS THE OUTPUT DATA PATH
BANK 0
MICROCONTROLLER
RAM
DISPLAY
BANK 4
013aaa422
Fig 41. Example of bank selection in 1:4 multiplex mode
In Figure 41 an example is shown for 1:4 multiplex drive mode where the displayed data is read from the first four rows of the memory (bank 0), while the transmitted data is stored in the second four rows of the memory (bank 4) which is currently not accessed for the reading. Therefore different content can be loaded into the first and second four RAM rows which will be immediately displayed on the LCD by switching it with the output-bank-select command (see Figure 42).
columns display RAM columns/segment outputs (S) 0 0 1 rows display RAM rows/ backplane outputs (BP) 2 3 4 5 6 7 input RAM bank
013aaa424
1
2
3
4
5
6
7
55 56 57 58 59
output RAM bank
to the LCD
to the RAM
Fig 42. Example of the input-bank-select and the output-bank-select command with multiplex drive mode 1:4
7.9.2.1
Input-bank-select The input-bank-select command (see Table 18 on page 10) loads display data into the display RAM in accordance with the selected LCD drive configuration.
* In static drive mode, an individual content can be stored in each RAM bank (bank 0 to
bank 7 which corresponds to row 0 to row 7).
* In 1:2 multiplex drive mode, individual content for RAM bank 0 (row 0 and row 1),
RAM bank 2 (row 2 and row 3), RAM bank 4 (row 4 and 5) and RAM bank 6 (row 6 and row 7) can be stored.
* In 1:4 multiplex drive mode individual content can be stored in RAM bank 0 (row 0 to
row 3) and RAM bank 4 (row 4 to row 7). The input-bank-select command works independently to the output-bank-select.
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7.9.2.2
Output-bank-select The output-bank-select command (see Table 19 on page 10) selects the display RAM transferring it to the display register in accordance with the selected LCD drive configuration.
* In the static drive mode it is possible to request the content of RAM bank 1 (row 1) to
RAM bank 7 (row 7) for display instead of the default RAM bank 0 (row 0).
* In 1:2 multiplex drive mode, the content of RAM bank 2 (row 2 and row 3) or of RAM
bank 4 (row 4 and row 5) or of RAM bank 6 (row 6 and row 7) may be selected instead of the default RAM bank 0 (row 0 and row 1).
* In 1:4 multiplex drive mode, the content of RAM bank 4 (row 4, 5, 6, and 7) may be
selected instead of RAM bank 0 (row 0, 1, 2, and 3). The output-bank-select command works independently to the input-bank-select.
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8. I2C-bus interface characteristics
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
8.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Figure 43).
SDA
SCL data line stable; data valid change of data allowed
mba607
Fig 43. Bit transfer
8.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change of the data line, while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH change of the data line while the clock is HIGH is defined as the STOP condition (P). The START and STOP conditions are shown in Figure 44.
SDA
SDA
SCL S START condition P STOP condition
SCL
mbc622
Fig 44. Definition of START and STOP conditions
8.3 System configuration
A device generating a message is a transmitter; a device receiving a message is the receiver. The device that controls the message is the master; and the devices which are controlled by the master are the slaves. The system configuration is shown in Figure 45.
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MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
mga807
Fig 45. System configuration
8.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge cycle.
* A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
* Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
* The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration).
* A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is shown in Figure 46.
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition clock pulse for acknowledgement
mbc602
1
2
8
9
Fig 46. Acknowledgement on the I2C-bus
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8.5 I2C-bus controller
The PCA9620 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from PCA9620 are the acknowledge signals and the temperature readout byte of the selected device.
8.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines.
8.7 I2C-bus slave address
Device selection depends on the I2C-bus slave address. Four different I2C-bus slave addresses can be used to address the PCA9620 (see Table 32).
Table 32. Bit slave address I2C slave address Slave address 7 MSB 0 1 1 1 0 A1 A0 6 5 4 3 2 1 0 LSB R/W
The least significant bit of the slave address byte is bit R/W. Bit 1 and bit 2 of the slave address are defined by connecting the inputs A0 and A1 to either VSS (logic 0) or VDD (logic 1). Therefore, four instances of PCA9620 can be distinguished on the same I2C-bus.
8.8 I2C-bus protocol
R/W = 0 slave address AA CR S01110 0A 10 OS control byte RAM/command byte M AS B L SP B
EXAMPLES a) transmit two bytes of RAM data S01110AA0A01 10 A RAM DATA A RAM DATA AP
b) transmit two command bytes S01110 AA 0A10 10 A COMMAND A00 A COMMAND AP
c) transmit one command byte and two RAM date bytes S01110 AA 0A10 10 A COMMAND A01 A RAM DATA A RAM DATA AP
013aaa293
Fig 47. I2C-bus protocol write mode
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The I2C-bus protocol is shown in Figure 47. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of the four PCA9620 slave addresses available. All PCA9620's with the corresponding A1 and A0 level acknowledge in parallel to the slave address, but all PCA9620 with the alternative A1 and A0 levels ignore the whole I2C-bus transfer. After acknowledgement, a control byte follows which defines if the next byte is RAM or command information. The control byte also defines if the next byte is a control byte or further RAM or command data.
Table 33. Bit 7 Control byte description Symbol CO 0 1 6 RS 0 1 5 to 0 Value Description continue bit last control byte control bytes continue register selection command register data register not relevant
MSB 7
6
5
4
3
2
1
LSB 0
CO RS
not relevant
mgl753
Fig 48. Control byte format
In this way it is possible to configure the device and then fill the display RAM with little overhead. The display bytes are stored in the display RAM at the address specified by the data pointer. The acknowledgement after each byte is made only by the (A0 and A1) addressed PCA9620. After the last display byte, the I2C-bus master issues a STOP condition (P). Alternatively a START may be issued to RESTART an I2C-bus access. In case that a temperature readout (byte TD[7:0]) is made the R/W bit must be logic 1 and then the next data byte following is provided by the PCA9620 as shown in Figure 49.
R/W = 1 slave address
S01110 M AA 1AS 10 B
temperature readout byte
L SAP B
acknowledge from PCA9620
acknowledge from master
013aaa294
Fig 49. I2C-bus protocol read mode
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9. Internal circuitry
VDD1 A0, A1, T1, T2, CLK VSS VLCD VSS BP0 to BP7, S0 to S59 VSS
013aaa295
T3, VLCD, SDA, SCL, VDD1, VDD2
Fig 50. Device protection diagram
PCA9620
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10. Limiting values
CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
Table 34. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD1 VDD2 IDD1 IDD2 VLCD IDD(LCD) Vi Parameter supply voltage 1 supply voltage 2 supply current 1 supply current 2 LCD supply voltage LCD supply current input voltage on pins CLK, SDA, SCL, A0, A1, T1, T2, T3 on pins S0 to S59, BP0 to BP7 on pins SDA, CLK IO ISS Ptot P/out VESD Ilu Tstg Tamb
[1] [2] [3] [4]
Conditions analog and digital charge pump analog and digital charge pump
Min -0.5 -0.5 -50 -50 -0.5 -50 -0.5
Max +6.5 +6.5 +50 +50 +10 +50 +6.5
Unit V V mA mA V mA V
II VO
input current output voltage
-10 -0.5 -0.5 -10 -50 HBM CDM
[1] [2] [3] [4]
+10 +10 +6.5 +10 +50 400 100 4000 1500 100 +150 +105
mA V V mA mA mW mW V V mA C C
output current ground supply current total power dissipation power dissipation per output electrostatic discharge voltage latch-up current storage temperature ambient temperature operating device
-65 -40
Pass level; Human Body Model (HBM), according to Ref. 6 "JESD22-A114". Pass level; Charged-Device Model (CDM), according to Ref. 7 "JESD22-C101". Pass level; latch-up testing according to Ref. 8 "JESD78" at maximum ambient temperature (Tamb(max)). According to the NXP store and transport requirements (see Ref. 10 "NX3-00092") the devices have to be stored at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %. For long term storage products divergent conditions are described in that document.
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11. Static characteristics
Table 35. Static characteristics VDD1 = 2.5 V to 5.5 V; VDD2 = 2.5 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = -40 C to +105 C; unless otherwise specified. Symbol Supplies VDD1 VDD2 VLCD VLCD supply voltage 1 supply voltage 2 LCD supply voltage LCD voltage variation VDD2 VDD1 VLCD VDD2 VLCD = 5.0 V to 9.0 V Tamb = -40 C to -10 C Tamb = -10 C to +70 C Tamb = +70 C to +105 C IDD(pd) IDD1 IDD2 power-down mode supply on pin VDD1 current supply current 1 supply current 2 fosc = 9.6 kHz charge pump off; external VLCD charge pump on; internal VLCD IDD(LCD) ILCD(pd) RO LCD supply current power-down LCD current output resistance external VLCD external VLCD of charge pump (driving capabilities) charge pump set to 2 x VDD2; Iload = 3 mA (on pin VLCD) charge pump set to 3 x VDD2; Iload = 2 mA (on pin VLCD) Tacc temperature accuracy readout temperature error; VDD1 = 5.0 V Tamb = -40 C to +105 C Tamb = 27 C Logic VI VIL VIH VO VOH VOL IOH IOL VPOR IL input voltage LOW-level input voltage HIGH-level input voltage output voltage HIGH-level output voltage on pin CLK LOW-level output voltage on pin CLK HIGH-level output current output source current; VOH = 4.6 V; VDD = 5 V; on pin CLK LOW-level output current power-on reset voltage leakage current Vi = VDD or VSS; on pins CLK, A1, A0, T1, T2, T3 output sink current; VOL = 0.4 V; VDD = 5 V; on pin CLK
[10] [11] [8] [4][5] [4][6] [4][7] [3][4] [3][4] [1] [2]
Parameter
Conditions
Min 2.5 2.5 2.5 -100 -70 -100 0.2 2.0
Typ 1.0 100 0.5 250 125 12 0.85 3.2
Max 5.5 5.5 9.0 +100 +70 +100 3.0 200 3.0 550 250 35 1.6 4.5
Unit V V V mV mV mV A A A A A A k k
[4][5]
[9]
-6 -4
-
+6 +4
C C
VSS - 0.5 on pins CLK, A1, A0 on pins CLK, A1, A0 0.7VDD -0.5 0.8VDD 1 1 0
VDD + 0.5 V 0.3VDD 0.2VDD 1.6 V V V V mA mA V A
VDD + 0.5 V
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Table 35. Static characteristics ...continued VDD1 = 2.5 V to 5.5 V; VDD2 = 2.5 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = -40 C to +105 C; unless otherwise specified. Symbol I2C-bus; VI VIL VIH VO IOL IL LCD outputs VO RO output voltage variation output resistance on pins BP0 to BP7 on pins S0 to S59 VLCD = 7 V; on pins BP0 to BP7 VLCD = 7 V; on pins S0 to S59
[1] [2] [3] [4] [5] [6]
[12] [13] [14] [14]
Parameter pins SDA and SCL input voltage LOW-level input voltage HIGH-level input voltage output voltage LOW-level output current leakage current
Conditions
Min
Typ
Max 5.5 0.3VDD 5.5 +15 +15 1.5 3
Unit V V V V mA A mV mV k k
VSS - 0.5 pins SCL, SDA pins SCL, SDA pins SCL, SDA VOL = 0.4 V; VDD = 5 V; on pin SDA VI = VDD or VSS
[11]
0.7VDD -0.5 3 -15 -15 0.3 0.6
0 0.8 1.5
When supplying external VLCD it must be VLCD VDD2. Also when using the internal charge pump to generate a certain VLCD, VPR[7:0] must be set to a value that the voltage is higher than VDD2 (see Section 7.4.3 on page 31). Calibrated at testing stage with VDD1 = VDD2 = 5.0 V. VLCD temperature compensation is disabled. Display is disabled; I2C-bus inactive; temperature measurement disabled. The typical value is defined at VDD1 = VDD2 = 5.0 V, VLCD = 7.0 V and 30 C. Temperature measurement enabled; 1:8 multiplex drive mode; 14 bias; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; inputs at VSS or VDD; internal clock with the default prescale factor; I2C-bus inactive. VDD2 = 5.0 V; charge pump set to 2 x VDD2; VPR[7:0] set for VLCD = 7.0 V; 1:8 multiplex drive mode; 14 bias; temperature measurement enabled; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. External supplied VLCD = 7.0 V; 1:8 multiplex drive mode; 14 bias; temperature measurement enabled; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive. VDD2 = 5.0 V; charge pump set to 2 x VDD2; VPR[7:0] set for VLCD = 9.0 V; display disabled; CPF (see Table 22 on page 11) set logic 0. VDD2 = 4.0 V; charge pump set to 3 x VDD2; VPR[7:0] set for VLCD = 9.0 V; display disabled; CPF (see Table 22 on page 11) set logic 0.
[7] [8] [9]
[10] If VDD1 > VPOR then no reset occurs. [11] In case of an ESD event, the value may increase slightly. [12] Variation between any 2 backplanes on a given voltage level; static measured. [13] Variation between any 2 segments on a given voltage level; static measured. [14] Outputs measured one at a time.
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8.3 VLCD (V) 7.8
(3)
001aan026
7.3
(1)
6.8
6.3
(2)
5.8 -50
0
50
100 temperature (C)
150
(1) VPR[7:0] = 85h. (2) VPR[7:0] = 64h. (3) VPR[7:0] = A4h. Temperature compensation disabled.
Fig 51. Typical VLCD with respect to temperature
120 IDD1 (A) 100
001aan023
80
60 -40
0
40
80 temperature (C)
120
VDD1 = 5.0 V.
Fig 52. Typical IDD1 with respect to temperature
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300 IDD2 (A) 260
001aan024
220
180
140
100 -40
0
40
80 temperature (C)
120
Charge pump set to 2 x VDD2; VLCD = 7.0 V; VDD1 = VDD2 = 5.0 V.
Fig 53. Typical IDD2 with respect to temperature
140 ILCD (A) 120
001aan025
100
80 -40
0
40
80 temperature (C)
120
VLCD = 7.0 V, external supplied; VDD1 = VDD2 = 5.0 V; display enabled, but no display attached.
Fig 54. Typical ILCD with respect to temperature
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12. Dynamic characteristics
Table 36. Dynamic characteristics VDD1 = 2.5 V to 5.5 V; VDD2 = 2.5 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 9.0 V; Tamb = -40 C to +105 C; unless otherwise specified. Symbol fosc fclk(ext) tclk(H) tclk(L) fSCL tBUF tHD;STA tSU;STA tVD;DAT tVD;ACK tLOW tHIGH tf tr Cb tSU;DAT tHD;DAT tSU;STO tw(spike)
[1] [2] [3] [4] [5]
Parameter oscillator frequency external clock frequency HIGH-level clock time LOW-level clock time SCL frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition data valid time data valid acknowledge time LOW period of the SCL clock HIGH period of the SCL clock fall time rise time capacitive load for each bus line data set-up time data hold time set-up time for STOP condition spike pulse width
Conditions on pin CLK; see Table 17 on page 9 external clock source used
[1][2]
Min 8160 450 33 33 1.3 0.6 0.6
[4] [5]
Typ 9600 -
Max 11040 14500 400 0.9 0.9 0.3 0.3 400 50
Unit Hz Hz s s kHz s s s s s s s s s pF ns ns s ns
Timing characteristics: I2C-bus[3]
1.3 0.6
of both SDA and SCL signals of both SDA and SCL signals
100 0 0.6 -
Internal calibration made with OTP so that the maximum variation is 15 % over whole temperature and voltage range. The typical fosc generates a typical frame frequency of 200 Hz when the default frequency division factor is used (see Section 7.5.3 on page 39). The typical value is defined at VDD1 = VDD2 = 5.0 V and 30 C. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. tVD;DAT = minimum time for valid SDA output following SCL LOW. tVD;ACK = time for acknowledgement signal from SCL LOW to SDA output LOW.
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1/fclk tclk(H) tclk(L) 0.7 VDD CLK 0.3 VDD
013aaa296
Fig 55. Driver timing waveforms
protocol
START condition (S) tSU;STA
bit 7 MSB (A7) tLOW tHIGH
bit 6 (A6)
bit 0 (R/W)
acknowledge (A)
STOP condition (P)
1/f SCL
SCL tBUF tr tf
SDA
tHD;STA
tSU;DAT
tHD;DAT
tVD;DAT
tVD;ACK
tSU;STO
013aaa417
Fig 56. I2C-bus timing waveforms
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13. Package outline
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1
c
y X A 60 61 41 40 Z E
e E HE wM bp pin 1 index 80 1 20 ZD bp D HD wM B vM B vM A 21 detail X Lp L A A2 A1 (A 3)
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.16 0.04 A2 1.5 1.3 A3 0.25 bp 0.27 0.13 c 0.18 0.12 D (1) 12.1 11.9 E (1) 12.1 11.9 e 0.5 HD HE L 1 Lp 0.75 0.30 v 0.2 w 0.15 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7 o 0
o
14.15 14.15 13.85 13.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT315-1 REFERENCES IEC 136E15 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Fig 57. Package outline SOT315-1 (LQFP80)
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14. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
14.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
14.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
14.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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14.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 58) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 37 and 38
Table 37. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 38. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 58.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 58. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
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15. Abbreviations
Table 39. Acronym AEC CDM DC EPROM ESD HBM I2C IC LCD LSB MSB MSL MUX OTP PCB POR RC RAM RMS SCL SDA SMD Abbreviations Description Automotive Electronics Council Charged-Device Model Direct Current Erasable Programmable Read-Only Memory ElectroStatic Discharge Human Body Model Inter-Integrated Circuit bus Integrated Circuit Liquid Crystal Display Least Significant Bit Most Significant Bit Moisture Sensitivity Level Multiplexer One Time Programmable Printed-Circuit Board Power-On Reset Resistance-Capacitance Random Access Memory Root Mean Square Serial CLock line Serial DAta line Surface Mount Device
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16. References
[1] [2] [3] [4] [5] [6] [7] [8] [9] AN10365 -- Surface mount reflow soldering description AN10853 -- ESD and EMC sensitivity of IC IEC 60134 -- Rating systems for electronic tubes and valves and analogous semiconductor devices IEC 61340-5 -- Protection of electronic devices from electrostatic phenomena IPC/JEDEC J-STD-020D -- Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices JESD22-A114 -- Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) JESD22-C101 -- Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components JESD78 -- IC Latch-Up Test JESD625-A -- Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices
[10] NX3-00092 -- NXP store and transport requirements [11] SNV-FA-01-02 -- Marking Formats Integrated Circuits [12] UM10204 -- I2C-bus specification and user manual
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17. Revision history
Table 40. Revision history Release date 20101209 Data sheet status Product data sheet Change notice Supersedes Document ID PCA9620 v.1
-
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18. Legal information
18.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
18.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
18.3 Disclaimers
Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications -- This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be
PCA9620
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 1 -- 9 December 2010
68 of 71
NXP Semiconductors
PCA9620
Universal LCD driver for low multiplex rates
Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
18.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
19. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
PCA9620
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 1 -- 9 December 2010
69 of 71
NXP Semiconductors
PCA9620
Universal LCD driver for low multiplex rates
20. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Functional description . . . . . . . . . . . . . . . . . . . 5 7.1 Commands of PCA9620 . . . . . . . . . . . . . . . . . . 5 7.1.1 Command: initialize . . . . . . . . . . . . . . . . . . . . . 5 7.1.2 Command: OTP-refresh . . . . . . . . . . . . . . . . . . 6 7.1.3 Command: oscillator-ctrl . . . . . . . . . . . . . . . . . . 6 7.1.4 Command: charge-pump-ctrl . . . . . . . . . . . . . . 7 7.1.5 Command: temp-msr-ctrl . . . . . . . . . . . . . . . . . 7 7.1.6 Command: set-VPR-MSB and set-VPR-LSB . . 7 7.1.7 Command: display-enable . . . . . . . . . . . . . . . . 8 7.1.8 Command: set-MUX-mode . . . . . . . . . . . . . . . . 8 7.1.9 Command: set-bias-mode . . . . . . . . . . . . . . . . 8 7.1.10 Command: load-data-pointer . . . . . . . . . . . . . . 8 7.1.11 Command: frame-frequency . . . . . . . . . . . . . . . 9 7.1.12 Bank select commands . . . . . . . . . . . . . . . . . 10 7.1.12.1 Command: input-bank-select . . . . . . . . . . . . . 10 7.1.12.2 Command: output-bank-select . . . . . . . . . . . . 10 7.1.13 Command: write-RAM-data . . . . . . . . . . . . . . 11 7.1.14 Command: temp-read. . . . . . . . . . . . . . . . . . . 11 7.1.15 Command: invmode_CPF_ctrl . . . . . . . . . . . . 11 7.1.16 Command: temp-filter . . . . . . . . . . . . . . . . . . . 12 7.2 Possible display configurations . . . . . . . . . . . 12 7.3 Start-up and shut-down. . . . . . . . . . . . . . . . . . 14 7.3.1 Power-On Reset (POR) . . . . . . . . . . . . . . . . . 14 7.3.2 Recommended start-up sequences . . . . . . . . 16 7.3.3 Recommended power-down sequences . . . . 18 7.4 LCD voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.4.1 LCD voltage selector . . . . . . . . . . . . . . . . . . . 20 7.4.1.1 Electro-optical performance . . . . . . . . . . . . . . 22 7.4.2 LCD drive mode waveforms . . . . . . . . . . . . . . 23 7.4.2.1 Static drive mode . . . . . . . . . . . . . . . . . . . . . . 23 7.4.2.2 1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 24 7.4.2.3 1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 26 7.4.2.4 1:6 Multiplex drive mode. . . . . . . . . . . . . . . . . 27 7.4.2.5 1:8 Multiplex drive mode. . . . . . . . . . . . . . . . . 29 7.4.3 VLCD generation . . . . . . . . . . . . . . . . . . . . . . . 31 7.4.4 External VLCD supply . . . . . . . . . . . . . . . . . . . 32 7.4.5 Charge pump driving capability . . . . . . . . . . . 33 7.4.6 Charge pump frequency settings and power efficiency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.4.7 7.4.8 7.5 7.5.1 7.5.2 7.5.3 7.6 7.7 7.8 7.9 7.9.1 7.9.1.1 7.9.1.2 7.9.1.3 7.9.1.4 7.9.1.5 7.9.2 7.9.2.1 7.9.2.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 17 18 18.1 18.2 18.3 18.4 Temperature readout . . . . . . . . . . . . . . . . . . . Temperature compensation of VLCD . . . . . . . . Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal oscillator . . . . . . . . . . . . . . . . . . . . . . External clock. . . . . . . . . . . . . . . . . . . . . . . . . Timing and frame frequency . . . . . . . . . . . . . Backplane outputs . . . . . . . . . . . . . . . . . . . . . Segment outputs . . . . . . . . . . . . . . . . . . . . . . Display register . . . . . . . . . . . . . . . . . . . . . . . Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . RAM filling in static drive mode . . . . . . . . . . . RAM filling in 1:2 multiplex drive mode . . . . . RAM filling in 1:4 multiplex drive mode . . . . . RAM filling in 1:6 multiplex drive mode . . . . . RAM filling in 1:8 multiplex drive mode . . . . . Bank selection . . . . . . . . . . . . . . . . . . . . . . . . Input-bank-select . . . . . . . . . . . . . . . . . . . . . . Output-bank-select. . . . . . . . . . . . . . . . . . . . . I2C-bus interface characteristics . . . . . . . . . . Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . START and STOP conditions. . . . . . . . . . . . . System configuration . . . . . . . . . . . . . . . . . . . Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . I2C-bus slave address . . . . . . . . . . . . . . . . . . I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . Limiting values . . . . . . . . . . . . . . . . . . . . . . . . Static characteristics . . . . . . . . . . . . . . . . . . . Dynamic characteristics. . . . . . . . . . . . . . . . . Package outline. . . . . . . . . . . . . . . . . . . . . . . . Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering. . . . . . . . . . . . . . . Wave soldering . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering . . . . . . . . . . . . . . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . References. . . . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 35 36 38 38 38 39 39 40 40 40 41 42 43 43 44 45 46 47 48 49 49 49 49 50 51 51 51 51 53 54 55 59 61 62 62 62 62 63 65 66 67 68 68 68 68 69
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PCA9620
All information provided in this document is subject to legal disclaimers.
(c) NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 1 -- 9 December 2010
70 of 71
NXP Semiconductors
PCA9620
Universal LCD driver for low multiplex rates
19 20
Contact information. . . . . . . . . . . . . . . . . . . . . 69 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 December 2010 Document identifier: PCA9620

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